One or more embodiments relate to a nonvolatile memory device and, more particularly, to a method of programming a nonvolatile memory device which is capable of performing operations using a reduced number of latches in a page buffer.
A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer unit, etc. The memory cell array includes a plurality of word lines extending in rows, a plurality of bit lines extending in columns, and a plurality of cell strings corresponding to the respective bit lines.
The row decoder is coupled to a string selection line, word lines, and a common source line and is placed on one side of the memory cell array. The page buffer unit coupled to the plurality of bit lines is placed on the other side of the memory cell array.
Recently, to further increase the degree of integration of flash memory cells, active research is being done on a multi-bit cell capable of storing data of plural bits in a single memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing a single bit is called a single level cell (SLC).
In a nonvolatile memory device, the number of latches for sensing data or storing program data is gradually increasing.
In a nonvolatile memory device using MLCs, it is important to narrow a distribution of the threshold voltages of the cells. To control the distribution, a program operation is performed in various manners, such as double verification and reprogram.
In a nonvolatile memory device including MLCs, to meet the number of increased programs, the number of latches of a page buffer for storing data is also increased. Furthermore, since the page buffer occupies a large area in the nonvolatile memory device, the area occupied by the page buffer is increased with an increase in the number of latches.